1. Field of Invention
The invention relates to a device comprising a delta-sigma modulator, and a switching member connected to the latter amplifier, in particular for processing the input signal with low oversampling ratio (OSR) and high signal-to-noise ratio (SNR).
2. Brief Description of the Related Art
Due to the fact that a switching amplifier, in particular a MOSFET output stage in the switching mode, only a very low power in the off state (“Cut-off state”) and saturation state consumes, it offers better efficiency than linear-amplifier. In theory, power is consumed only when switching between these states.
Often a PDM (Pulse Duration Modulation)—module and/or DSM (delta-sigma) modulator module, which converts the high-resolution signal to a signal having a low resolution (1-bit pulse train) at a much higher frequency, is directly connected before a switching amplifier (digital amplifier) in the switching operation. The power amplifier is often followed by a low pass reconstruction filter, which restores the amplified baseband signal.
Delta-sigma modulators, referred to as “DSM”, shape the signal-to-noise ratio (SNR) so as to push away the noise in the frequency range of the signal. In the reference book “Understanding Delta-Sigma Data Converters” by Richard Schreier, Gabor Temes, Wiley Interscience Publication 2005, ISBN 0-471-46585-2 will be presented more conventional DSM-structures. The structures described here aimed at baseband signals with low sampling rates. Relatively high oversampling ratios with high order of the DSM (e.g. over the 16) are used to guarantee an acceptable SNR of the output signals. In the case of a very high sampling rate of the baseband signal (over the 2 MSps (Mega-samples per second)), however, only low oversampling ratios are technically feasible for the power amplification. The electrical characteristics of the most power amplifier transistors cause for high frequency input pulses to have a strong deterioration of the quality of the output signal and the gain efficiency.
The low sampling rate (RSR; Reduced sampling rate) designed DSM (DSM-RSR) provides the same SNR magnitude with a much lower OSR. In the essay “A Reduced-Sample-Rate Sigma-Delta-Pipeline ADC Architecture for High-Speed High-Resolution Applications” by Vahid Majidzadeh, Omid Shoaei published in IEICE Transactions 89-C (6): 692-701 (2006), there are shown two practical examples for RSR loop filter. The RSR-DSM 4th and 6th order provides, compared to the conventional DSM-loop filters, a higher SNR for a low OSR.
The use of multi-bit quantization in the DSM increases the SNR and improves the stability of the DSM as discussed in the article “Delta-Sigma modulator: modeling, design and application” of George Bouropoulos published in Imperial College Press, 2003, ISBN 1-86094-369-1 and as discussed in the doctoral thesis “Stability Analysis and Design of bandpass sigma delta modulator” by Jürgen van Engelen, Eindhoven University of Technology, 1999, ISBN 90-386-1580-9. However, each bit of the multi-bit output of the DSM requires a separate power amplifier per channel with weighted power supply. The above solution is very costly and is not recommended for technical aspects.
A fundamental remedy to this drawback is to place a parallel-to-serial converter at the output of the multi-bit DSM and before the MOSFET output stage in the switching mode CDA and thus feed a 1-bit pulse stream in the CDA. This concept is explained briefly in the thesis “Stability Analysis and Design of bandpass sigma delta modulator” by Jürgen van Engelen, whereas this concept, for example, is used in some patent applications such as GB-A-2438774, GB-A-2435559 or GB-A-2406008.
To find the optimal coefficients for the loop filter in the DSM, a search algorithm can be used, as this for example is explained in the essay “An Automatic Coefficient Design Methodology for High-order Bandpass Sigma-Delta modulator with single-Stage Structure” by Hwi-Ming Wang published in IEEE Transactions on Circuits and Systems II, July 2006, pages 580-584 or by Wan-Rone Liou, “A Low-Power Delta-sigma modulator Multi-Bit with Data Weighted Averaging Technique”, Workshop on Consumer Electronics and Signal Processing, 2005, Taiwan.
In the prior art a DSM is often used with a multi-bit signal at the output and often signals audio are to amplified, so there is still a significantly lower frequency range, lower bandwidth and correspondingly lower sampling rates as well. The solutions described in the patent applications GB-A-2438774, GB-A-2435559 or GB-A-2406008 the P/S conversion has a strong influence on the structure of the loop filter and its parameters. Furthermore, in these patent applications GB-A-2,438,774, GB-A-2,435,559 or GB-A 2,406,008 the control of flipping requires a complex control/logic.
Furthermore, from U.S. Pat. No. 5,815,102 a digital-to-analog (D/A)-converter, in particular a Delta-Sigma-Converter used for audio signals and a reduced switching is known. In the human hearing audio frequencies lies in a range of 16 Hz to 20 kHz. Such a D/A converter is considered to be particularly useful for such hearing aids, which—in order to receive an ambient sound—comprising an audio receiver or receivers having an analog-to-digital converter to convert the sound sequences or sound in a digital signal lower rate and high resolution, having a digital processing circuitry to modify the quality of the digital signal showing a low-rate and high resolution, having an interpolator to convert the digital signal showing a low-rate and high resolution in a signal showing high definition and a medium rate, and having a digital-to-analog converter to convert back the modified digital signal showing a medium rate and high resolution into an analog sound. To make a digital-to-analog (D/A)-converter available, which has a low power consumption due to a reduction in the number of output signal transitions and while a low bias is maintained, according to U.S. Pat. No. 5,815,102, in the hearing aid a duty cycle demodulator formatted a digital signal showing low resolution and a high rate in a predetermined format of a low transition rate. For this purpose a multi-bit value corresponding to each input or input value of the digital signal showing a medium resolution and medium rate is determined and the values thus determined are outputted as a digital signal of low resolution and high rate. For example, the duty cycle demodulator store a value corresponding to each possible input value of the digital signal having medium resolution and medium rate (for example, in ROM) and look up the corresponding stored value for each inputted digital signal having medium resolution and medium rate. The conversion of the input values into output values is done by so-called “format” of the input signal, which is performed by looking up the stored values. In this alternate format grow odd cycles from the right and even cycles from the left.
Finally, from U.S. 2010/0066580 A1, an audio digital-to-analog (D/A)-converter is known, which converts digital audio signals into analog audio signals. Oversampling techniques are typically used in an audio D/A-converter in order to improve the accuracy of the analog output signal, so that it accurately represents the digital signal at the input of the D/A converter. The method used in U.S. 2010/0066580 A1 requires a table having a plurality of sequences for each quantization levels of the input signal and in each case have a positive and negative sequence. In addition, each alternating between sequences with positive and negative “common mode energy” (common mode energy), the sequences in the same “set” all begin with the same binary value, and all ends with the same binary value. Since these 2 bits per sequence are already established, a higher clock frequency of the output signal is required, whereas in consideration of low-frequency audio signals in the U.S. 2010/0066580 A1 this does not affect a hindrance.
The fundamental problem is the realization of high frequencies in the output stage. In principle, the highest possible quantization in the DSM for a better signal quality (SNR) was desired at the output, i.e. a highest possible resolution of the quantizer and hence as many bits at the output of the DSM. However, the higher the quantization is the greater is the required frequency to drive the output stage (if the resolution of the output stage is lower than that of the quantizer as is given in the case under consideration).
Furthermore also the chip pads (more precisely, the Die-Pads) have a low-pass characteristic, whereas the cut-off frequency of this low pass depends on the chip technology used in each case. The higher the oversampling ratio (OSR) and thus the higher clock frequency of the pad are, the greater is the frequency range in which due to the low-pass characteristic in the Die-Pad the filtering of the pulses is problematic. A reduction in the over-sampling ratio (OSR) inevitably leads to a low power loss and signal distortion in the switching amplifier.
In summary it can be stated that in the prior art, considering the amplifying of audio signals, significantly lower range of the useful signal and sampling frequencies are present, so that the realization of the required frequencies even at high oversampling ratio (OSR) is rather straightforward. For power electronics higher frequencies (as in the audio range) are a major challenge, since—through higher switching frequencies—signal distortions arise at the input of the amplifier.